vault backup: 2024-01-05 23:30:32
This commit is contained in:
sweetbread
parent
71efdda03b
commit
334557968d
7
.obsidian/graph.json
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7
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.obsidian/workspace-mobile.json
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34
.obsidian/workspace-mobile.json
vendored
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@ -85,7 +85,7 @@
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"file": "Оглавление.md",
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@ -102,7 +102,7 @@
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"file": "Оглавление.md",
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@ -114,7 +114,7 @@
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"lastOpenFiles": [
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"X86/Общего назначения.md",
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"X86/Общего назначения.md",
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"X86.md",
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"X86/Общего назначения/Побитовый сдвиг, вращение/Untitled.md",
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"X86/Общего назначения/Побитовый сдвиг, вращение",
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"Оглавление.md",
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"Оглавление.md",
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"X86/Общего назначения/Логические/NOT.md",
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"X86/Общего назначения/Логические/XOR.md",
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"X86/Общего назначения/Логические/OR.md",
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"X86/Общего назначения/Логические/AND.md",
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"X86/Общего назначения/Логические",
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"X86.md",
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"X86/Общего назначения/Двоичные арифметические/CMP.md",
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"X86/Общего назначения/Двоичные арифметические/CMP.md",
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"X86/Общего назначения/Двоичные арифметические/NEG.md",
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"X86/Общего назначения/Двоичные арифметические/NEG.md",
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"X86/Общего назначения/Двоичные арифметические/ADC.md",
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"X86/Общего назначения/Двоичные арифметические/ADC.md",
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@ -165,20 +172,13 @@
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"FASM.md",
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"FASM.md",
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"X86/Общего назначения/Передачи данных/CWD,CDQ,CQO.md",
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"X86/Общего назначения/Передачи данных/CWD,CDQ,CQO.md",
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"X86/Общего назначения/Передачи данных/OUT.md",
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"X86/Общего назначения/Передачи данных/OUT.md",
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"X86/Общего назначения/Передачи данных/IN.md",
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"X86/Общего назначения/Передачи данных/POPA(D).md",
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"X86/Общего назначения/Передачи данных/PUSHA(D).md",
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"Общего назначения/Передачи данных/PUSHA(D).md",
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"Общего назначения",
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"Общего назначения",
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"Общего назначения/Передачи данных",
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"Общего назначения/Передачи данных",
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"X86/Общего назначения/Untitled.md",
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"Untitled",
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"Untitled",
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"Общегоы/Общего назначения",
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"Общегоы/Общего назначения",
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"Общегоы",
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"Общегоы",
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"Общегоы/Общего назначения/Передачи данных",
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"Общегоы/Общего назначения/Передачи данных",
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"Untitled.canvas",
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"Untitled.canvas",
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"Общего_назначения",
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"Общего_назначения"
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"X86/Общего назначения/Передачи данных",
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"X86/Общего назначения"
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]
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]
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}
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}
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@ -49,11 +49,11 @@
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## Логические команды
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## Логические команды
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| Команды | Описание |
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| Команды | Описание |
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| -------:|:------------------------------------ |
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| --------------------------------------------:|:------------------------------------ |
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| AND | Побитовое логическое И |
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| [AND](Общего%20назначения/Логические/AND.md) | Побитовое логическое И |
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| OR | Побитовое логическое ИЛИ |
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| [OR](Общего%20назначения/Логические/OR.md) | Побитовое логическое ИЛИ |
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| XOR | Побитовое логическое Исключающее ИЛИ |
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| [XOR](Общего%20назначения/Логические/XOR.md) | Побитовое логическое Исключающее ИЛИ |
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| NOT | Побитовое логическое НЕ |
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| [NOT](Общего%20назначения/Логические/NOT.md) | Побитовое логическое НЕ |
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## Команды побитового сдвига и вращения
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## Команды побитового сдвига и вращения
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| Команды | Описание |
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| Команды | Описание |
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26
X86/Общего назначения/Логические/AND.md
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26
X86/Общего назначения/Логические/AND.md
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@ -0,0 +1,26 @@
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| Opcode | Instruction | Op/En | 64-bit Mode | Compat/Leg Mode | Description |
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| ---------------- | ---------------- | ----- | ----------- | --------------- | ----------------------------------------- |
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| 24 ib | AND AL, imm8 | I | Valid | Valid | AL AND imm8. |
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| 25 iw | AND AX, imm16 | I | Valid | Valid | AX AND imm16. |
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| 25 id | AND EAX, imm32 | I | Valid | Valid | EAX AND imm32. |
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| REX.W + 25 id | AND RAX, imm32 | I | Valid | N.E. | RAX AND imm32 sign-extended to 64-bits. |
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| 80 /4 ib | AND r/m8, imm8 | MI | Valid | Valid | r/m8 AND imm8. |
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| REX + 80 /4 ib | AND r/m8\*, imm8 | MI | Valid | N.E. | r/m8 AND imm8. |
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| 81 /4 iw | AND r/m16, imm16 | MI | Valid | Valid | r/m16 AND imm16. |
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| 81 /4 id | AND r/m32, imm32 | MI | Valid | Valid | r/m32 AND imm32. |
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| REX.W + 81 /4 id | AND r/m64, imm32 | MI | Valid | N.E. | r/m64 AND imm32 sign extended to 64-bits. |
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| 83 /4 ib | AND r/m16, imm8 | MI | Valid | Valid | r/m16 AND imm8 (sign-extended). |
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| 83 /4 ib | AND r/m32, imm8 | MI | Valid | Valid | r/m32 AND imm8 (sign-extended). |
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| REX.W + 83 /4 ib | AND r/m64, imm8 | MI | Valid | N.E. | r/m64 AND imm8 (sign-extended). |
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| 20 /r | AND r/m8, r8 | MR | Valid | Valid | r/m8 AND r8. |
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| REX + 20 /r | AND r/m8\*, r8\* | MR | Valid | N.E. | r/m64 AND r8 (sign-extended). |
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| 21 /r | AND r/m16, r16 | MR | Valid | Valid | r/m16 AND r16. |
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| 21 /r | AND r/m32, r32 | MR | Valid | Valid | r/m32 AND r32. |
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| REX.W + 21 /r | AND r/m64, r64 | MR | Valid | N.E. | r/m64 AND r32. |
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| 22 /r | AND r8, r/m8 | RM | Valid | Valid | r8 AND r/m8. |
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| REX + 22 /r | AND r8*, r/m8\* | RM | Valid | N.E. | r/m64 AND r8 (sign-extended). |
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| 23 /r | AND r16, r/m16 | RM | Valid | Valid | r16 AND r/m16. |
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| 23 /r | AND r32, r/m32 | RM | Valid | Valid | r32 AND r/m32. |
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| REX.W + 23 /r | AND r64, r/m64 | RM | Valid | N.E. | r64 AND r/m64. |
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> \* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
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7
X86/Общего назначения/Логические/NOT.md
Normal file
7
X86/Общего назначения/Логические/NOT.md
Normal file
@ -0,0 +1,7 @@
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|||||||
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| Opcode | Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
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| ------------- | ----------- | ----- | ----------- | --------------- | -------------------------- |
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| F6 /2 | NOT r/m8 | M | Valid | Valid | Reverse each bit of r/m8. |
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| REX + F6 /2 | NOT r/m81 | M | Valid | N.E. | Reverse each bit of r/m8. |
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| F7 /2 | NOT r/m16 | M | Valid | Valid | Reverse each bit of r/m16. |
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| F7 /2 | NOT r/m32 | M | Valid | Valid | Reverse each bit of r/m32. |
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| REX.W + F7 /2 | NOT r/m64 | M | Valid | N.E. | Reverse each bit of r/m64. |
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26
X86/Общего назначения/Логические/OR.md
Normal file
26
X86/Общего назначения/Логические/OR.md
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| Opcode | Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
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| ---------------- | --------------- | ----- | ----------- | --------------- | ------------------------------- |
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| 0C ib | OR AL, imm8 | I | Valid | Valid | AL OR imm8. |
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| 0D iw | OR AX, imm16 | I | Valid | Valid | AX OR imm16. |
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| 0D id | OR EAX, imm32 | I | Valid | Valid | EAX OR imm32. |
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| REX.W + 0D id | OR RAX, imm32 | I | Valid | N.E. | RAX OR imm32 (sign-extended). |
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| 80 /1 ib | OR r/m8, imm8 | MI | Valid | Valid | r/m8 OR imm8. |
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| REX + 80 /1 ib | OR r/m8\*, imm8 | MI | Valid | N.E. | r/m8 OR imm8. |
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| 81 /1 iw | OR r/m16, imm16 | MI | Valid | Valid | r/m16 OR imm16. |
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| 81 /1 id | OR r/m32, imm32 | MI | Valid | Valid | r/m32 OR imm32. |
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| REX.W + 81 /1 id | OR r/m64, imm32 | MI | Valid | N.E. | r/m64 OR imm32 (sign-extended). |
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| 83 /1 ib | OR r/m16, imm8 | MI | Valid | Valid | r/m16 OR imm8 (sign-extended). |
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| 83 /1 ib | OR r/m32, imm8 | MI | Valid | Valid | r/m32 OR imm8 (sign-extended). |
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| REX.W + 83 /1 ib | OR r/m64, imm8 | MI | Valid | N.E. | r/m64 OR imm8 (sign-extended). |
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| 08 /r | OR r/m8, r8 | MR | Valid | Valid | r/m8 OR r8. |
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| REX + 08 /r | OR r/m8\*, r8\* | MR | Valid | N.E. | r/m8 OR r8. |
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| 09 /r | OR r/m16, r16 | MR | Valid | Valid | r/m16 OR r16. |
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| 09 /r | OR r/m32, r32 | MR | Valid | Valid | r/m32 OR r32. |
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| REX.W + 09 /r | OR r/m64, r64 | MR | Valid | N.E. | r/m64 OR r64. |
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| 0A /r | OR r8, r/m8 | RM | Valid | Valid | r8 OR r/m8. |
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| REX + 0A /r | OR r8\*, r/m8\* | RM | Valid | N.E. | r8 OR r/m8. |
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| 0B /r | OR r16, r/m16 | RM | Valid | Valid | r16 OR r/m16. |
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| 0B /r | OR r32, r/m32 | RM | Valid | Valid | r32 OR r/m32. |
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| REX.W + 0B /r | OR r64, r/m64 | RM | Valid | N.E. | r64 OR r/m64. |
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> \* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
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26
X86/Общего назначения/Логические/XOR.md
Normal file
26
X86/Общего назначения/Логические/XOR.md
Normal file
@ -0,0 +1,26 @@
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| Opcode | Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
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||||||
|
| ---------------- | ---------------- | ----- | ----------- | --------------- | -------------------------------- |
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||||||
|
| 34 ib | XOR AL, imm8 | I | Valid | Valid | AL XOR imm8. |
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| 35 iw | XOR AX, imm16 | I | Valid | Valid | AX XOR imm16. |
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| 35 id | XOR EAX, imm32 | I | Valid | Valid | EAX XOR imm32. |
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||||||
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| REX.W + 35 id | XOR RAX, imm32 | I | Valid | N.E. | RAX XOR imm32 (sign-extended). |
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||||||
|
| 80 /6 ib | XOR r/m8, imm8 | MI | Valid | Valid | r/m8 XOR imm8. |
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||||||
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| REX + 80 /6 ib | XOR r/m8\*, imm8 | MI | Valid | N.E. | r/m8 XOR imm8. |
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| 81 /6 iw | XOR r/m16, imm16 | MI | Valid | Valid | r/m16 XOR imm16. |
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||||||
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| 81 /6 id | XOR r/m32, imm32 | MI | Valid | Valid | r/m32 XOR imm32. |
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|
| REX.W + 81 /6 id | XOR r/m64, imm32 | MI | Valid | N.E. | r/m64 XOR imm32 (sign-extended). |
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||||||
|
| 83 /6 ib | XOR r/m16, imm8 | MI | Valid | Valid | r/m16 XOR imm8 (sign-extended). |
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||||||
|
| 83 /6 ib | XOR r/m32, imm8 | MI | Valid | Valid | r/m32 XOR imm8 (sign-extended). |
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||||||
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| REX.W + 83 /6 ib | XOR r/m64, imm8 | MI | Valid | N.E. | r/m64 XOR imm8 (sign-extended). |
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||||||
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| 30 /r | XOR r/m8, r8 | MR | Valid | Valid | r/m8 XOR r8. |
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||||||
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| REX + 30 /r | XOR r/m8\*, r8\* | MR | Valid | N.E. | r/m8 XOR r8. |
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||||||
|
| 31 /r | XOR r/m16, r16 | MR | Valid | Valid | r/m16 XOR r16. |
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||||||
|
| 31 /r | XOR r/m32, r32 | MR | Valid | Valid | r/m32 XOR r32. |
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||||||
|
| REX.W + 31 /r | XOR r/m64, r64 | MR | Valid | N.E. | r/m64 XOR r64. |
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||||||
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| 32 /r | XOR r8, r/m8 | RM | Valid | Valid | r8 XOR r/m8. |
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| REX + 32 /r | XOR r8\*, r/m8\* | RM | Valid | N.E. | r8 XOR r/m8. |
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| 33 /r | XOR r16, r/m16 | RM | Valid | Valid | r16 XOR r/m16. |
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| 33 /r | XOR r32, r/m32 | RM | Valid | Valid | r32 XOR r/m32. |
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||||||
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| REX.W + 33 /r | XOR r64, r/m64 | RM | Valid | N.E. | r64 XOR r/m64. |
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|
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|
> * In64-bit mode, r/m8 cannot been coded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
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75
X86/Общего назначения/Побитовый сдвиг, вращение/Untitled.md
Normal file
75
X86/Общего назначения/Побитовый сдвиг, вращение/Untitled.md
Normal file
@ -0,0 +1,75 @@
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**Opcode1**
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||||||
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||||||
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||Instruction|Op/En|64-Bit Mode|Compat/Leg Mode|Description|
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
|D0 /4|SAL r/m8, 1|M1|Valid|Valid|Multiply r/m8 by 2, once.|
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||||||
|
|REX + D0 /4|SAL r/m82, 1|M1|Valid|N.E.|Multiply r/m8 by 2, once.|
|
||||||
|
|D2 /4|SAL r/m8, CL|MC|Valid|Valid|Multiply r/m8 by 2, CL times.|
|
||||||
|
|REX + D2 /4|SAL r/m82, CL|MC|Valid|N.E.|Multiply r/m8 by 2, CL times.|
|
||||||
|
|C0 /4 ib|SAL r/m8, imm8|MI|Valid|Valid|Multiply r/m8 by 2, imm8 times.|
|
||||||
|
|REX + C0 /4 ib|SAL r/m82, imm8|MI|Valid|N.E.|Multiply r/m8 by 2, imm8 times.|
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|
|D1 /4|SAL r/m16, 1|M1|Valid|Valid|Multiply r/m16 by 2, once.|
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|
|D3 /4|SAL r/m16, CL|MC|Valid|Valid|Multiply r/m16 by 2, CL times.|
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|
|C1 /4 ib|SAL r/m16, imm8|MI|Valid|Valid|Multiply r/m16 by 2, imm8 times.|
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|
|D1 /4|SAL r/m32, 1|M1|Valid|Valid|Multiply r/m32 by 2, once.|
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|
|REX.W + D1 /4|SAL r/m64, 1|M1|Valid|N.E.|Multiply r/m64 by 2, once.|
|
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|
|D3 /4|SAL r/m32, CL|MC|Valid|Valid|Multiply r/m32 by 2, CL times.|
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|
|REX.W + D3 /4|SAL r/m64, CL|MC|Valid|N.E.|Multiply r/m64 by 2, CL times.|
|
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|
|C1 /4 ib|SAL r/m32, imm8|MI|Valid|Valid|Multiply r/m32 by 2, imm8 times.|
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|
|REX.W + C1 /4 ib|SAL r/m64, imm8|MI|Valid|N.E.|Multiply r/m64 by 2, imm8 times.|
|
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|
|D0 /7|SAR r/m8, 1|M1|Valid|Valid|Signed divide3 r/m8 by 2, once.|
|
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|
|REX + D0 /7|SAR r/m82, 1|M1|Valid|N.E.|Signed divide3 r/m8 by 2, once.|
|
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|
|D2 /7|SAR r/m8, CL|MC|Valid|Valid|Signed divide3 r/m8 by 2, CL times.|
|
||||||
|
|REX + D2 /7|SAR r/m82, CL|MC|Valid|N.E.|Signed divide3 r/m8 by 2, CL times.|
|
||||||
|
|C0 /7 ib|SAR r/m8, imm8|MI|Valid|Valid|Signed divide3 r/m8 by 2, imm8 times.|
|
||||||
|
|REX + C0 /7 ib|SAR r/m82, imm8|MI|Valid|N.E.|Signed divide3 r/m8 by 2, imm8 times.|
|
||||||
|
|D1 /7|SAR r/m16,1|M1|Valid|Valid|Signed divide3 r/m16 by 2, once.|
|
||||||
|
|D3 /7|SAR r/m16, CL|MC|Valid|Valid|Signed divide3 r/m16 by 2, CL times.|
|
||||||
|
|C1 /7 ib|SAR r/m16, imm8|MI|Valid|Valid|Signed divide3 r/m16 by 2, imm8 times.|
|
||||||
|
|D1 /7|SAR r/m32, 1|M1|Valid|Valid|Signed divide3 r/m32 by 2, once.|
|
||||||
|
|REX.W + D1 /7|SAR r/m64, 1|M1|Valid|N.E.|Signed divide3 r/m64 by 2, once.|
|
||||||
|
|D3 /7|SAR r/m32, CL|MC|Valid|Valid|Signed divide3 r/m32 by 2, CL times.|
|
||||||
|
|REX.W + D3 /7|SAR r/m64, CL|MC|Valid|N.E.|Signed divide3 r/m64 by 2, CL times.|
|
||||||
|
|C1 /7 ib|SAR r/m32, imm8|MI|Valid|Valid|Signed divide3 r/m32 by 2, imm8 times.|
|
||||||
|
|REX.W + C1 /7 ib|SAR r/m64, imm8|MI|Valid|N.E.|Signed divide3 r/m64 by 2, imm8 times|
|
||||||
|
|D0 /4|SHL r/m8, 1|M1|Valid|Valid|Multiply r/m8 by 2, once.|
|
||||||
|
|REX + D0 /4|SHL r/m82, 1|M1|Valid|N.E.|Multiply r/m8 by 2, once.|
|
||||||
|
|D2 /4|SHL r/m8, CL|MC|Valid|Valid|Multiply r/m8 by 2, CL times.|
|
||||||
|
|REX + D2 /4|SHL r/m82, CL|MC|Valid|N.E.|Multiply r/m8 by 2, CL times.|
|
||||||
|
|C0 /4 ib|SHL r/m8, imm8|MI|Valid|Valid|Multiply r/m8 by 2, imm8 times.|
|
||||||
|
|REX + C0 /4 ib|SHL r/m82, imm8|MI|Valid|N.E.|Multiply r/m8 by 2, imm8 times.|
|
||||||
|
|D1 /4|SHL r/m16,1|M1|Valid|Valid|Multiply r/m16 by 2, once.|
|
||||||
|
|D3 /4|SHL r/m16, CL|MC|Valid|Valid|Multiply r/m16 by 2, CL times.|
|
||||||
|
|C1 /4 ib|SHL r/m16, imm8|MI|Valid|Valid|Multiply r/m16 by 2, imm8 times.|
|
||||||
|
|D1 /4|SHL r/m32,1|M1|Valid|Valid|Multiply r/m32 by 2, once.|
|
||||||
|
|
||||||
|
**Opcode1**
|
||||||
|
|
||||||
|
| | Instruction | Op/En | 64-Bit Mode | Compat/Leg Mode | Description |
|
||||||
|
| ---------------- | --------------- | ----- | ----------- | --------------- | --------------------------------------- |
|
||||||
|
| REX.W + D1 /4 | SHL r/m64,1 | M1 | Valid | N.E. | Multiply r/m64 by 2, once. |
|
||||||
|
| D3 /4 | SHL r/m32, CL | MC | Valid | Valid | Multiply r/m32 by 2, CL times. |
|
||||||
|
| REX.W + D3 /4 | SHL r/m64, CL | MC | Valid | N.E. | Multiply r/m64 by 2, CL times. |
|
||||||
|
| C1 /4 ib | SHL r/m32, imm8 | MI | Valid | Valid | Multiply r/m32 by 2, imm8 times. |
|
||||||
|
| REX.W + C1 /4 ib | SHL r/m64, imm8 | MI | Valid | N.E. | Multiply r/m64 by 2, imm8 times. |
|
||||||
|
| D0 /5 | SHR r/m8,1 | M1 | Valid | Valid | Unsigned divide r/m8 by 2, once. |
|
||||||
|
| REX + D0 /5 | SHR r/m82, 1 | M1 | Valid | N.E. | Unsigned divide r/m8 by 2, once. |
|
||||||
|
| D2 /5 | SHR r/m8, CL | MC | Valid | Valid | Unsigned divide r/m8 by 2, CL times. |
|
||||||
|
| REX + D2 /5 | SHR r/m82, CL | MC | Valid | N.E. | Unsigned divide r/m8 by 2, CL times. |
|
||||||
|
| C0 /5 ib | SHR r/m8, imm8 | MI | Valid | Valid | Unsigned divide r/m8 by 2, imm8 times. |
|
||||||
|
| REX + C0 /5 ib | SHR r/m82, imm8 | MI | Valid | N.E. | Unsigned divide r/m8 by 2, imm8 times. |
|
||||||
|
| D1 /5 | SHR r/m16, 1 | M1 | Valid | Valid | Unsigned divide r/m16 by 2, once. |
|
||||||
|
| D3 /5 | SHR r/m16, CL | MC | Valid | Valid | Unsigned divide r/m16 by 2, CL times |
|
||||||
|
| C1 /5 ib | SHR r/m16, imm8 | MI | Valid | Valid | Unsigned divide r/m16 by 2, imm8 times. |
|
||||||
|
| D1 /5 | SHR r/m32, 1 | M1 | Valid | Valid | Unsigned divide r/m32 by 2, once. |
|
||||||
|
| REX.W + D1 /5 | SHR r/m64, 1 | M1 | Valid | N.E. | Unsigned divide r/m64 by 2, once. |
|
||||||
|
| D3 /5 | SHR r/m32, CL | MC | Valid | Valid | Unsigned divide r/m32 by 2, CL times. |
|
||||||
|
| REX.W + D3 /5 | SHR r/m64, CL | MC | Valid | N.E. | Unsigned divide r/m64 by 2, CL times. |
|
||||||
|
| C1 /5 ib | SHR r/m32, imm8 | MI | Valid | Valid | Unsigned divide r/m32 by 2, imm8 times. |
|
||||||
|
| REX.W + C1 /5 ib | SHR r/m64, imm8 | MI | Valid | N.E. | Unsigned divide r/m64 by 2, imm8 times. |
|
||||||
|
|
||||||
|
> 1. See the IA-32 Architecture Compatibility section below.
|
||||||
|
>
|
||||||
|
> 2. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
|
||||||
|
>
|
||||||
|
> 3. Not the same form of division as IDIV; rounding is toward negative infinity.
|
||||||
Loading…
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Reference in New Issue
Block a user